IDT5T93GL04 ii equivalent, 2.5v lvds 1:4 glitchless clock buffer terabuffer ii.
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Guaranteed low skew: <50ps (maximum) Very low duty cycle distortion: <100ps (maximum High sp.
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Clock distribution
Pin Assignment
GND PD FSEL VDD Q1 Q1 Q2 Q2 VDD SEL G GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 2.
The IDT5T93GL04 2.5V differential clock buffer is a user-selectable differential input to four LVDS outputs. The fanout from a differential input to four LVDS outputs reduces loading on the preceding driver and provides an efficient clock distributio.
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